Silicon Labs /Series1 /EFR32BG12P /EFR32BG12P332F1024GL125 /VDAC0 /STATUS

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Interpret as STATUS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0ENS)CH0ENS 0 (CH1ENS)CH1ENS 0 (CH0BL)CH0BL 0 (CH1BL)CH1BL 0 (CH0WARM)CH0WARM 0 (CH1WARM)CH1WARM 0 (OPA0APORTCONFLICT)OPA0APORTCONFLICT 0 (OPA1APORTCONFLICT)OPA1APORTCONFLICT 0 (OPA2APORTCONFLICT)OPA2APORTCONFLICT 0 (OPA0ENS)OPA0ENS 0 (OPA1ENS)OPA1ENS 0 (OPA2ENS)OPA2ENS 0 (OPA0WARM)OPA0WARM 0 (OPA1WARM)OPA1WARM 0 (OPA2WARM)OPA2WARM 0 (OPA0OUTVALID)OPA0OUTVALID 0 (OPA1OUTVALID)OPA1OUTVALID 0 (OPA2OUTVALID)OPA2OUTVALID

Description

Status Register

Fields

CH0ENS

Channel 0 Enabled Status

CH1ENS

Channel 1 Enabled Status

CH0BL

Channel 0 Buffer Level

CH1BL

Channel 1 Buffer Level

CH0WARM

Channel 0 Warm

CH1WARM

Channel 1 Warm

OPA0APORTCONFLICT

OPA0 Bus Conflict Output

OPA1APORTCONFLICT

OPA1 Bus Conflict Output

OPA2APORTCONFLICT

OPA2 Bus Conflict Output

OPA0ENS

OPA0 Enabled Status

OPA1ENS

OPA1 Enabled Status

OPA2ENS

OPA2 Enabled Status

OPA0WARM

OPA0 Warm Status

OPA1WARM

OPA1 Warm Status

OPA2WARM

OPA2 Warm Status

OPA0OUTVALID

OPA0 Output Valid Status

OPA1OUTVALID

OPA1 Output Valid Status

OPA2OUTVALID

OPA2 Output Valid Status

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